whitemike889/e200_opensource

master

e200_opensource

Grade	Name	Complexity	Churn	Issues
B	riscv-tools\riscv-fesvr\scripts\install.sh		1	15
A	riscv-tools\fpga_test4sim\coremark4sim\core_list_join.c	61	1	1
A	riscv-tools\riscv-fesvr\scripts\vcs-version.sh		1	8
A	riscv-tools\riscv-fesvr\fesvr\elf2hex.cc	9	1	-
A	riscv-tools\riscv-isa-sim\debug_rom\debug_rom_defines.h	0	1	-
A	riscv-tools\fpga_test4sim\dhrystone4sim\dhry_1.c	11	1	-
A	riscv-tools\riscv-isa-sim\dummy_rocc\dummy_rocc_test.c	1	1	-
A	riscv-tools\riscv-fesvr\fesvr\elfloader.h	0	1	-
A	riscv-tools\riscv-isa-sim\riscv\cachesim.h	16	1	3
A	riscv-tools\fpga_test4sim\coremark4sim\core_portme.h	2	1	-
A	riscv-tools\riscv-isa-sim\riscv\common.h	0	1	-
A	riscv-tools\riscv-fesvr\fesvr\htif.cc	48	1	2
A	riscv-tools\riscv-isa-sim\riscv\debug_module.cc	109	1	6
A	riscv-tools\fpga_test4sim\dhrystone4sim\dhry_stubs.c	3	1	-
A	riscv-tools\riscv-isa-sim\riscv\devices.cc	8	1	-
A	riscv-tools\riscv-fesvr\fesvr\htif_hexwriter.cc	15	1	-
A	riscv-tools\fpga_test4sim\coremark4sim\core_main.c	56	1	1
A	riscv-tools\fpga_test4sim\coremark4sim\core_state.c	54	1	1
A	riscv-tools\riscv-fesvr\fesvr\context.cc	8	1	-
A	riscv-tools\riscv-fesvr\fesvr\htif_hexwriter.h	3	1	-