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Issues
A
techlibs\quicklogic\ql_dsp_simd.cc
28 2 2
A
techlibs\quicklogic\qlf_k6n10f\generate_bram_types_sim.py
7 1 -
A
techlibs\quicklogic\synth_quicklogic.cc
92 2 4
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techlibs\sf2\synth_sf2.cc
55 1 2
B
techlibs\xilinx\cells_xtra.py
43 1 19
A
techlibs\xilinx\synth_xilinx.cc
204 1 3
A
techlibs\xilinx\tests\bram1.sh
 2 1
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techlibs\xilinx\tests\bram2.sh
 2 -
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techlibs\xilinx\tests\test_dsp48_model.sh
 2 -
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techlibs\xilinx\tests\test_dsp48a1_model.sh
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A
techlibs\xilinx\tests\test_dsp_model.sh
 2 -
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techlibs\xilinx\xilinx_dffopt.cc
95 1 2
A
tests\aiger\run-test.sh
 2 1
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tests\arch\anlogic\run-test.sh
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tests\arch\ecp5\run-test.sh
 1 -
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tests\arch\efinix\run-test.sh
 1 -
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tests\arch\gatemate\gen_luttrees.py
7 1 -
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tests\arch\gatemate\run-test.sh
 1 -
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tests\arch\gowin\run-test.sh
 1 -
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tests\arch\ice40\run-test.sh
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